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eusci_b_i2c_ex5_slaveMultipleSlave.c
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32 #include "driverlib.h"
33 //******************************************************************************
34 // MSP430F5xx_6xx Demo - USCI_B0 I2C 4 Hardware I2C slaves
35 //
36 // Description: This demo connects two MSP430's via the I2C bus.
37 // This code configures the MSP430 USCI to be addressed as 4 independent I2C
38 // slaves. Each slave has its owm interrupt flag and data variable to store
39 // incoming data.
40 //
41 // Tested on MSP430F67791A
42 // /|\ /|\
43 // 10k 10k
44 // slave | | master
45 // ----------------- | | -----------------
46 // -|XIN P2.6/UCB0SDA|<-|----+->|P2.6/UCB0SDA XIN|-
47 // | | | | |
48 // -|XOUT | | | XOUT|-
49 // | P2.5/UCB0SCL|<-+------>|P2.5/UCB0SCL |
50 // | | | |
51 // | | | |
52 //
53 //******************************************************************************
54 uint8_t RXData0 = 0;
55 uint8_t RXData1 = 0;
56 uint8_t RXData2 = 0;
57 uint8_t RXData3 = 0;
58 
59 void main(void)
60 {
61  WDT_A_hold(WDT_A_BASE);
62 
63  //Configure Pins for I2C (UCB0SCL, UCB0SDA)
64  //Set P2.5 and P2.6 as Module Function Input
65  GPIO_setAsPeripheralModuleFunctionInputPin(
66  GPIO_PORT_P2,
67  GPIO_PIN5 + GPIO_PIN6
68  );
69 
70  // eUSCI configuration
71  //SLAVE0 own address is 0x0A+ enable
72  EUSCI_B_I2C_initSlaveParam initSlave0Param = {0};
73  initSlave0Param.slaveAddress = 0x0A;
74  initSlave0Param.slaveAddressOffset = EUSCI_B_I2C_OWN_ADDRESS_OFFSET0;
75  initSlave0Param.slaveOwnAddressEnable = EUSCI_B_I2C_OWN_ADDRESS_ENABLE;
76  EUSCI_B_I2C_initSlave(EUSCI_B0_BASE, &initSlave0Param);
77 
78  //SLAVE1 own address is 0x0B+ enable
79  EUSCI_B_I2C_initSlaveParam initSlave1Param = {0};
80  initSlave1Param.slaveAddress = 0x0B;
81  initSlave1Param.slaveAddressOffset = EUSCI_B_I2C_OWN_ADDRESS_OFFSET1;
82  initSlave1Param.slaveOwnAddressEnable = EUSCI_B_I2C_OWN_ADDRESS_ENABLE;
83  EUSCI_B_I2C_initSlave(EUSCI_B0_BASE, &initSlave1Param);
84 
85  //SLAVE2 own address is 0x0C+ enable
86  EUSCI_B_I2C_initSlaveParam initSlave2Param = {0};
87  initSlave2Param.slaveAddress = 0x0C;
88  initSlave2Param.slaveAddressOffset = EUSCI_B_I2C_OWN_ADDRESS_OFFSET2;
89  initSlave2Param.slaveOwnAddressEnable = EUSCI_B_I2C_OWN_ADDRESS_ENABLE;
90  EUSCI_B_I2C_initSlave(EUSCI_B0_BASE, &initSlave2Param);
91 
92  //SLAVE3 own address is 0x0D+ enable
93  EUSCI_B_I2C_initSlaveParam initSlave3Param = {0};
94  initSlave3Param.slaveAddress = 0x0D;
95  initSlave3Param.slaveAddressOffset = EUSCI_B_I2C_OWN_ADDRESS_OFFSET3;
96  initSlave3Param.slaveOwnAddressEnable = EUSCI_B_I2C_OWN_ADDRESS_ENABLE;
97  EUSCI_B_I2C_initSlave(EUSCI_B0_BASE, &initSlave3Param);
98 
99  EUSCI_B_I2C_enable(EUSCI_B0_BASE);
100 
101  EUSCI_B_I2C_clearInterrupt(EUSCI_B0_BASE,
102  EUSCI_B_I2C_RECEIVE_INTERRUPT0 +
103  EUSCI_B_I2C_RECEIVE_INTERRUPT1 +
104  EUSCI_B_I2C_RECEIVE_INTERRUPT2 +
105  EUSCI_B_I2C_RECEIVE_INTERRUPT3
106  );
107 
108  //receive interrupt enable
109  EUSCI_B_I2C_enableInterrupt(EUSCI_B0_BASE,
110  EUSCI_B_I2C_RECEIVE_INTERRUPT0 +
111  EUSCI_B_I2C_RECEIVE_INTERRUPT1 +
112  EUSCI_B_I2C_RECEIVE_INTERRUPT2 +
113  EUSCI_B_I2C_RECEIVE_INTERRUPT3
114  );
115 
116  __bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
117  __no_operation();
118 }
119 
120 #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
121 #pragma vector=USCI_B0_VECTOR
122 __interrupt
123 #elif defined(__GNUC__)
124 __attribute__((interrupt(USCI_B0_VECTOR)))
125 #endif
126 void USCIB0_ISR(void)
127 {
128  switch(__even_in_range(UCB0IV, USCI_I2C_UCBIT9IFG))
129  {
130  case USCI_NONE: // No interrupts break;
131  break;
132  case USCI_I2C_UCALIFG: // Arbitration lost
133  break;
134  case USCI_I2C_UCNACKIFG: // NAK received (master only)
135  break;
136  case USCI_I2C_UCSTTIFG: // START condition detected with own address (slave mode only)
137  break;
138  case USCI_I2C_UCSTPIFG: // STOP condition detected (master & slave mode)
139  break;
140  case USCI_I2C_UCRXIFG3: // RXIFG3
141  RXData3 = EUSCI_B_I2C_slaveGetData(EUSCI_B0_BASE);
142  break;
143  case USCI_I2C_UCTXIFG3: // TXIFG3
144  break;
145  case USCI_I2C_UCRXIFG2: // RXIFG2
146  RXData2 = EUSCI_B_I2C_slaveGetData(EUSCI_B0_BASE);
147  break;
148  case USCI_I2C_UCTXIFG2: // TXIFG2
149  break;
150  case USCI_I2C_UCRXIFG1: // RXIFG1
151  RXData1 = EUSCI_B_I2C_slaveGetData(EUSCI_B0_BASE);
152  break;
153  case USCI_I2C_UCTXIFG1: // TXIFG1
154  break;
155  case USCI_I2C_UCRXIFG0: // RXIFG0
156  RXData0 = EUSCI_B_I2C_slaveGetData(EUSCI_B0_BASE);
157  break;
158  case USCI_I2C_UCTXIFG0: // TXIFG0
159  break;
160  case USCI_I2C_UCBCNTIFG: // Byte count limit reached (UCBxTBCNT)
161  break;
162  case USCI_I2C_UCCLTOIFG: // Clock low timeout - clock held low too long
163  break;
164  case USCI_I2C_UCBIT9IFG: // Generated on 9th bit of a transmit (for debugging)
165  break;
166  default:
167  break;
168  }
169 }
170 
USCIB0_ISR
void USCIB0_ISR(void)
Definition: eusci_b_i2c_ex5_slaveMultipleSlave.c:126
main
void main(void)
Definition: eusci_b_i2c_ex5_slaveMultipleSlave.c:59
RXData2
uint8_t RXData2
Definition: eusci_b_i2c_ex5_slaveMultipleSlave.c:56
RXData0
uint8_t RXData0
Definition: eusci_b_i2c_ex5_slaveMultipleSlave.c:54
RXData3
uint8_t RXData3
Definition: eusci_b_i2c_ex5_slaveMultipleSlave.c:57
RXData1
uint8_t RXData1
Definition: eusci_b_i2c_ex5_slaveMultipleSlave.c:55
__no_operation
__no_operation()